1 p/n:pm0370 rev. 3.1, may 19, 2004 32m-bit (4m x 8 / 2m x 16) mask rom features ? bit organization - 4m x 8 (byte mode) - 2m x 16 (word mode) fast access time - random access:70ns (max.) for 3.0v~3.6v 90ns (max.) for 2.7v~3.6v current - operating:40ma - standby:15ua supply voltage - 2.7v~3.6v package - 44 pin sop (500mil) - 48 pin tsop (12mm x 20mm) - 44 pin tsop (type ii) order information part no. access time package mx23l3210mc-10 100ns 44 pin sop mx23l3210mc-12 120ns 44 pin sop mx23l3210mc-15 150ns 44 pin sop mx23l3210tc-70 70ns 48 pin tsop mx23l3210tc-90 90ns 48 pin tsop mx23l3210tc-10 100ns 48 pin tsop mx23l3210tc-12 120ns 48 pin tsop mx23l3210tc-15 150ns 48 pin tsop mx23l3210rc-70 70ns 48 pin tsop (reverse type) mx23l3210rc-90 90ns 48 pin tsop (reverse type) mx23l3210rc-10 100ns 48 pin tsop (reverse type) mx23l3210rc-12 120ns 48 pin tsop (reverse type) mx23l3210rc-15 150ns 48 pin tsop (reverse type) mx23l3210yc-10 100ns 44 pin tsop mx23l3210yc-12 120ns 44 pin tsop pin description symbol pin function a0~a20 address inputs d0~d14 data outputs d15/a-1 d15 (word mode)/ lsb address (byte mode) ce chip enable input oe output enable input byte word/ byte mode selection vcc power supply pin vss ground pin nc no connection pin configuration 44 sop/ 44 tsop mode selection ce oe byte d15/a-1 d0~d7 d8~d15 mode power h x x x high z high z - stand-by l h x x high z high z - active l l h output d0~d7 d8~d15 word active l l l input d0~d7 high z byte active 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 nc a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce vss oe d0 d8 d1 d9 d2 d10 d3 d11 a20 a19 a8 a9 a10 a11 a12 a13 a14 a15 a16 byte vss d15/a-1 d7 d14 d6 d13 d5 d12 d4 vcc mx23l3210 mx23l3210
2 p/n:pm0370 rev. 3.1, may 19, 2004 mx23l3210 48 tsop (normal type) 48 tsop (reverse type) byte a16 a15 a14 a13 a12 a11 a10 a9 a8 a19 vss a20 a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vss vss d15/a-1 d7 d14 d6 d13 d5 d12 d4 vcc vcc nc d11 d3 d10 d2 d9 d1 d8 d0 oe vss vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 mx23l3210 (reverse tpye) byte a16 a15 a14 a13 a12 a11 a10 a9 a8 a19 vss a20 a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vss vss d15/a-1 d7 d14 d6 d13 d5 d12 d4 vcc vcc nc d11 d3 d10 d2 d9 d1 d8 d0 oe vss vss 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 mx23l3210 (normal type)
3 p/n:pm0370 rev. 3.1, may 19, 2004 mx23l3210 address buffer memory array sense amplifier word/ byte output buffer d0 d15/(d7) a0/(a-1) a20 ce byte oe absolute maximum ratings item symbol ratings voltage on any pin relative to vss vin -0.3v to 3.9v ambient operating temperature topr 0 c to 70 c storage temperature tstg -65 c to 125 c block diagram dc characteristics (ta = 0 c ~ 70 c, vcc = 2.7v~3.6v) item symbol min. max. conditions output high voltage voh 2.3v - ioh = -0.4ma output low voltage vol - 0.4v iol = 1.6ma input high voltage vih 2.1v vcc+0.3v input low voltage vil -0.3v 0.2xvcc input leakage current ili - 5ua 0v, vcc output leakage current ilo - 5ua 0v, vcc operating current icc1 - 40ma trc = 120ns, all output open standby current (ttl) istb1 - 1ma ce = vih standby current (cmos) istb2 - 15ua ce>vcc-0.2v input capacitance cin - 10pf ta = 25 c, f = 1mhz output capacitance cout - 10pf ta = 25 c, f = 1mhz
4 p/n:pm0370 rev. 3.1, may 19, 2004 mx23l3210 ac characteristics (ta = 0 c ~ 70 c, vcc = 3.0v~3.6v) item symbol 23l3210-70 23l3210-90 23l3210-10 23L3210-12 23l3210-15 min. max. min. max. min. max. min. max. min. max. read cycle time trc 70ns - 90ns - 100ns - 120ns - 150ns - address access time taa - 70ns - 90ns - 100ns - 120ns - 150ns chip enable access time tace - 70ns - 90ns - 100ns - 120ns - 150ns output enable time toe - 35ns - 45ns - 50ns - 60ns - 70ns output hold after address toh 0ns - 0ns - 0ns - 0ns - 0ns - output high z delay thz - 20ns - 20ns - 20ns - 20ns - 20ns ac test conditions input pulse levels 0.4v~2.4v input rise and fall times 10ns input timing level 1.4v output timing level 1.4 output load see figure timing diagram random read note:no output loading is present in tester load board. active loading is used and under software programming control. output loading capacitance includes load board's and all stray capacitance. dout c<100pf iol (load)=1.6ma ioh (load)=-0.4ma note:output high-impedance delay (thz) is measured from oe going high, and this parameter guaranteed by design over the full voltage and temperature operating range - not tested. tace taa toh thz add add add add ce# oe# data valid valid valid trc toe
5 p/n:pm0370 rev. 3.1, may 19, 2004 mx23l3210 package information
6 p/n:pm0370 rev. 3.1, may 19, 2004 mx23l3210
7 p/n:pm0370 rev. 3.1, may 19, 2004 mx23l3210
8 p/n:pm0370 rev. 3.1, may 19, 2004 mx23l3210
9 p/n:pm0370 rev. 3.1, may 19, 2004 mx23l3210 revision history revision description page date 2.5 ac characteristics toh 10ns-->0ns p4 jan/29/1999 2.6 add 120ns (max.) for 3.0v~3.6v ; 150ns(max.) for 2.7v~3.6v p1 dec/24/1999 dc characteristics standby current (istb2):5ua-->15ua p1,3 ac characteristics 120ns for 3.0v~3.6v p4 2.7 1. added access time:100ns p1,4 jun/28/2001 2. modify package information p5,6 2.8 1. added 44-pin tsop(ii) p1,7 jul/17/2001 2.9 1. added access time:70ns & 90ns p1,4 may/14/2002 3.0 modify package information p5~8 no v/21/2002 3.1 change 2.7~3.6v 150ns-->2.7~3.6v 90ns p1 may/19/2004
mx23l3210 m acronix i nternational c o., l td . headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office : tel:+32-2-456-8020 fax:+32-2-456-8021 hong kong office : tel:+86-755-834-335-79 fax:+86-755-834-380-78 japan office : kawasaki office : tel:+81-44-246-9100 fax:+81-44-246-9105 osaka office : tel:+81-6-4807-5460 fax:+81-6-4807-5461 singapore office : tel:+65-6346-5505 fax:+65-6348-8096 taipei office : tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-262-8887 fax:+1-408-262-8810 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.
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